`timescale 1ns/1ps
//in wrapper ,all control signals active high

module ram_dp_d256_w96_wrapper (clka,clkb,wea,web,cena,cenb,addra,addrb,dina,dinb,douta,doutb,ram_dp_cfg_register);//2021/8/28
  input  clka;
  input  clkb;
  input [11:0] ram_dp_cfg_register;
  input  wea;//write enable,active high
  input  web; 
  input  cena;//2021/8/28
  input  cenb;//2021/8/28
  input [7:0] addra;
  input [7:0] addrb;
  input [95:0] dina;
  input [95:0] dinb;
  output [95:0] douta;//rdata
  output [95:0] doutb;

ram_dp_d256_w96 U_ram_dp_d256_w96(
.CENYA(),
.WENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(douta),
.QB(doutb),
.SOA(),
.SOB(),
.CLKA(clka),
.CENA(cena),//2021/8/28
.WENA(~wea),
.AA(addra),
.DA(dina),
.CLKB(clkb),
.CENB(cenb),//2021/8/28
.WENB(~web),
.AB(addrb),
.DB(dinb),
.EMAA(ram_dp_cfg_register[11:9]),
.EMAWA(ram_dp_cfg_register[8:7]),
.EMASA(ram_dp_cfg_register[6]),
.EMAB(ram_dp_cfg_register[5:3]),
.EMAWB(ram_dp_cfg_register[2:1]),
.EMASB(ram_dp_cfg_register[0]),
.TENA(1'b1),
.TCENA(1'b1),
.TWENA(1'b1),
.TAA(8'b0),
.TDA(96'b0),
.TENB(1'b1),
.TCENB(1'b1),
.TWENB(1'b1),
.TAB(8'b0),
.TDB(96'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1) 
);
endmodule
